VHDL Factorial calculator -

VHDL Factorial calculator -

i attempting create 16-bit factorial calculator unsigned binary number. in doing have created info path , state machine

a.) outputs final value of 1 if value input 0

b.) displays , overflow flag if input on 8!

c.) calculates value factorial if value input less 8 , not zero.

the scheme seems fall apart if value input on 3 yet still not overflow. think issue somewhere in test3, update 1, update 2 in state machine. help explain going wrong?

state machine:

library ieee; utilize ieee.std_logic_1164.all; entity fact_16_ctrlv2 port( go : in std_logic; clk : in std_logic; clr : in std_logic; overflow : in std_logic; numeqcnt : in std_logic; factzero : in std_logic; flag: out std_logic; xload : out std_logic; cntmux : out std_logic; cntload : out std_logic; factload : out std_logic; factmux : out std_logic; finalload : out std_logic; finalmuxselect: out std_logic; decimalpoint: out std_logic ); end fact_16_ctrlv2; --}} end of automatically maintained section architecture fact_16_ctrlv2 of fact_16_ctrlv2 type state_type (start, input, test1, test2, test3, update1, update2, update3, done); signal present_state, next_state: state_type; begin sreg: process(clk, clr) begin if clr='1' present_state <= start; elsif clk'event , clk='1' present_state <= next_state; end if; end process; c1: process(present_state, go, overflow, factzero, numeqcnt) begin case present_state when start => if go = '1' next_state <= input; else next_state <= start; end if; when input => next_state <= test1; when test1 => if factzero= '1' next_state <= done; else next_state <= test2; end if; when test2 => if overflow = '1' next_state <= done; else next_state <= update3; end if; when update3 => next_state <= test3; when test3 => if numeqcnt = '1' next_state <= done; else next_state <= update1; end if; when update1 => next_state <= update2; when update2 => next_state <= test3; when done => next_state <= done; when others => null; end case; end process; c2: process(present_state, overflow, numeqcnt, factzero) begin xload<= '0'; flag <= '0'; cntmux <= '0'; cntload<= '0'; factload<='0'; factmux<='0'; finalload <='0'; finalmuxselect<='0'; decimalpoint<='0'; case present_state when input => xload<='1'; --cntmux<='1'; --cntload<='1'; when test2 => if overflow ='1' flag <= '1'; finalmuxselect<='0'; finalload<='1'; factload <='1'; decimalpoint <='1'; end if; when test1 => if factzero ='1' flag <= '1'; finalmuxselect <='1'; finalload <='1'; end if; when update3 => cntmux<='1'; cntload<='1'; factmux<= '1'; factload<= '1'; when test3 => if numeqcnt ='1' finalmuxselect<='0'; --finalload<='1'; factload <='1'; cntload<='1'; factmux<='0'; else end if; when update1 => factmux<='0'; factload<='1'; when update2 => cntmux<='0'; cntload<='1'; --factload<='1'; when done => finalload<='1'; when others => null; end case; end process; end fact_16_ctrlv2;

data path

library ieee; utilize ieee.std_logic_1164.all; entity fact_16_dp port( clr : in std_logic; clk : in std_logic; x : in std_logic_vector(3 downto 0); overflow : out std_logic; finalfact : out std_logic_vector(15 downto 0); cntload, cntmult, factload, factmult, xload, finalload :in std_logic; equalone, numcnt : out std_logic; finalmuxselect, flagin: in std_logic ); end fact_16_dp; --}} end of automatically maintained section architecture fact_16_dp of fact_16_dp -- component declaration of "mult16b(mult16b)" unit defined in -- file: "./../src/multiplier.vhd" component mult16b port( : in std_logic_vector(15 downto 0); b : in std_logic_vector(15 downto 0); p : out std_logic_vector(15 downto 0)); end component; all: mult16b utilize entity work.mult16b(mult16b); -- component declaration of "comp(comp)" unit defined in -- file: "./../src/comparitor.vhd" component comp generic( n : integer := 8); port( x : in std_logic_vector(n-1 downto 0); y : in std_logic_vector(n-1 downto 0); gt : out std_logic; eq : out std_logic; lt : out std_logic); end component; all: comp utilize entity work.comp(comp); -- component declaration of "adder(adder)" unit defined in -- file: "./../src/adder.vhd" component adder generic( n : integer := 8); port( : in std_logic_vector(n-1 downto 0); b : in std_logic_vector(n-1 downto 0); y : out std_logic_vector(n-1 downto 0)); end component; all: adder utilize entity work.adder(adder); -- component declaration of "reg(reg)" unit defined in -- file: "./../src/reg.vhd" component reg generic( n : integer := 8); port( load : in std_logic; clk : in std_logic; clr : in std_logic; d : in std_logic_vector(n-1 downto 0); q : out std_logic_vector(n-1 downto 0)); end component; all: reg utilize entity work.reg(reg); -- component declaration of "mux2g(mux2g)" unit defined in -- file: "./../src/mux21.vhd" component mux2g generic( n : integer); port( : in std_logic_vector(n-1 downto 0); b : in std_logic_vector(n-1 downto 0); s : in std_logic; y : out std_logic_vector(n-1 downto 0)); end component; all: mux2g utilize entity work.mux2g(mux2g); -- component declaration of "mux4g(mux4g)" unit defined in -- file: "./../src/mux4to1.vhd" component mux4g generic( n : integer); port( : in std_logic_vector(n-1 downto 0); b : in std_logic_vector(n-1 downto 0); c : in std_logic_vector(n-1 downto 0); s : in std_logic_vector(1 downto 0); y : out std_logic_vector(n-1 downto 0)); end component; all: mux4g utilize entity work.mux4g(mux4g); --signal cntload, cntmult, numcnt, factload, factmult, xload, numload, equalone, finalload :std_logic; signal adderout, cntregout, cntregin, x2 :std_logic_vector(3 downto 0); signal xin, factregin, factregout, overin, factmout, checkzero, numregout, flag, finalmuxout, cntregoutb :std_logic_vector(15 downto 0); begin x2 <= x; xin <= "000000000000" & x2; --change 4 bit number input 16 bit number cntregoutb <= "000000000000" & cntregout; --change count 4 bit value 16 bit value flag <= "000000000000000" & flagin; cntreg : reg --4-bit counter register generic map( n => 4 ) port map( load => cntload, clk => clk, clr => clr, d => cntregin, --not in drawing q => cntregout ); factreg : reg --16-bit fact register generic map( n => 16 ) port map( load => factload, clk => clk, clr => clr, d => factregin, q => factregout ); --numreg : reg --16-bit num register --generic map( --n => 16 --) --port map( --load => numload, --clk => clk, --clr => clr, --d => xin, --q => numregout --); xreg : reg --4-bit initial x vlaue register generic map( n => 4 ) port map( load => xload, clk => clk, clr => clr, d => x, --x(3:0) q => x2 ); finalreg : reg --16-bit final fact register generic map( n => 16 ) port map( load => finalload, clk => clk, clr => clr, d => finalmuxout, q => finalfact ); cntmux : mux2g --4-bit cnt mux generic map( n => 4 ) port map( b => "0001", --initial value set => adderout, --value after initial run through s => cntmult, y => cntregin --cntregin not in drawing ); factmux : mux2g --16-bit fact mux generic map( n => 16 ) port map( b => "0000000000000001", --initial value set => factmout, --value after initial run through s => factmult, y => factregin ); add1 : adder --increment counter 4-bit generic map( n => 4 ) port map( => cntregout, --add 1 b => "0001", --1 y => adderout --out of adder ); multiplier : mult16b --multiply cnt , fact 16-bit port map( => factregout, b => cntregoutb, --cnt plus 12 zeros 16-bit p => factmout --multiplier out ); greater8 : comp --16-bit check x overflow if greater 8 generic map( n => 16 ) port map( x => xin, --check value 8 y => "0000000000001000", gt => overflow --send overflow flag --eq => eq, --lt => lt ); check0 : comp --16-bit check x not equal 0 generic map( n => 16 ) port map( x => xin, y => "0000000000000000", --gt => gt, eq => equalone --lt => lt ); numeqcnt : comp --16-bit check if num equals cnt generic map( n => 16 ) port map( x => xin, y => cntregoutb, --need 16 bit --gt => gt, eq => numcnt --not in drawing --lt => lt ); finalmux: mux2g generic map( n => 16 ) port map( => factregout, b => flag, s => finalmuxselect, y => finalmuxout ); end fact_16_dp;

connected

------------------------------------------------------------------------------- -- -- title : fact_16 -- design : lab4 -- author : -- company : -- ------------------------------------------------------------------------------- -- -- file : c:\my_designs\lab4\lab4\src\fact_16.vhd -- generated : tue oct 14 16:40:38 2014 -- : interface description file -- : itf2vhdl ver. 1.22 -- ------------------------------------------------------------------------------- -- -- description : -- ------------------------------------------------------------------------------- --{{ section below comment automatically maintained -- , may overwritten --{entity {fact_16} architecture {fact_16}} library ieee; utilize ieee.std_logic_1164.all; entity fact_16 port( go : in std_logic; clk : in std_logic; clr : in std_logic; x : in std_logic_vector(3 downto 0); overflowb : out std_logic; factout : out std_logic_vector(15 downto 0) ); end fact_16; architecture fact_16 of fact_16 -- component declaration of "fact_16_dp(fact_16_dp)" unit defined in -- file: "./../src/fact_16_dp.vhd" component fact_16_dp port( clr : in std_logic; clk : in std_logic; x : in std_logic_vector(3 downto 0); overflow : out std_logic; finalfact : out std_logic_vector(15 downto 0); cntload : in std_logic; cntmult : in std_logic; factload : in std_logic; factmult : in std_logic; xload : in std_logic; finalload : in std_logic; equalone : out std_logic; numcnt : out std_logic; finalmuxselect : in std_logic; flagin : in std_logic); end component; all: fact_16_dp utilize entity work.fact_16_dp(fact_16_dp); -- component declaration of "fact_16_ctrlv2(fact_16_ctrlv2)" unit defined in -- file: "./../src/fact_16_ctrlv2.vhd" component fact_16_ctrlv2 port( go : in std_logic; clk : in std_logic; clr : in std_logic; overflow : in std_logic; numeqcnt : in std_logic; factzero : in std_logic; flag : out std_logic; xload : out std_logic; cntmux : out std_logic; cntload : out std_logic; factload : out std_logic; factmux : out std_logic; finalload : out std_logic; finalmuxselect : out std_logic; decimalpoint : out std_logic); end component; all: fact_16_ctrlv2 utilize entity work.fact_16_ctrlv2(fact_16_ctrlv2); signal overflow, numeqcnt, factzero, xload, cntmux, cntload, factload, flag, factmux, numload, finalload: std_logic; signal finalmuxselect: std_logic; begin dpath : fact_16_dp port map( clr => clr, clk => clk, x => x, overflow => overflow, finalfact => factout, cntload => cntload, cntmult => cntmux, factload => factload, factmult => factmux, xload => xload, finalload => finalload, equalone => factzero, numcnt => numeqcnt, finalmuxselect => finalmuxselect, flagin => flag ); cunit : fact_16_ctrlv2 port map( go => go, clk => clk, clr => clr, overflow => overflow, numeqcnt => numeqcnt, factzero => factzero, flag => flag, xload => xload, cntmux => cntmux, cntload => cntload, factload => factload, factmux => factmux, finalload => finalload, finalmuxselect => finalmuxselect, decimalpoint => overflowb ); end fact_16;

vhdl