for-generate inside process vhdl -

for-generate inside process vhdl -

i know not possible write for-generate within process want accomplish functionality presented code.it address decoder. help appreciated.

the next code gives syntax error : "syntax error near generate"

library ieee; utilize ieee.std_logic_1164.all; utilize ieee.numeric_std.all; entity address_decoder generic (cam_depth: integer := 8); port (in_address: in std_logic_vector(cam_depth-1 downto 0); out_address: out std_logic_vector(2**cam_depth-1 downto 0); clk : in std_logic; rst: in std_logic ); end address_decoder; architecture behavioral of address_decoder begin decode_process: process(clk,rst) begin if(clk'event , clk='1') if (rst = '1') out_address <= (others => '0'); else name: in 0 10 generate if (i = to_integer(unsigned(in_address))) out_address(i) <= '1'; else out_address(i) <= '0'; end if; end generate name; end if; end if; end process; end behavioral;

your decoder binary one-hot encoder downstream register. can extract encoder , set function

function bin2onehot(value : std_logic_vector) homecoming std_logic_vector variable result : std_logic_vector(2**value'length - 1 downto 0) := (others => '0'); begin result(2 ** to_integer(unsigned(value))) := '1'; homecoming result; end function;

and register:

process(clk) begin if rising_edge(clk) if (rst = '1') out_address <= (others => '0'); else out_address <= bin2onehot(in_address); end if; end if; end process;

you can spare rst sensitivity list, because it's synchronous reset.

vhdl