Interpreting a Generalized Makefile -

Interpreting a Generalized Makefile -

i came across code , having hard time grasping it. code in makefile generalized having problem shortcuts

cc = gcc cflags = -wall deps = primes.h obj = go.o primes.o %.o: %.c $(deps) $(cc) $(cflags) -c -o $@ $< go: $(obj) gcc $(cflags) -o $@ $^ target %.o mean ? if wish come in target write ? dependency mean ? $@ $< mean ? $@ $^ mean ?

the %.o applies files ending in .o suffix, %.c applies files ending in .c suffix. $< first item in dependencies list. special macros $@ , $^, left , right sides of rule having :, respectively, create overall compilation rule more general.

thus,

go: $(obj) gcc $(cflags) -o $@ $^

expands to:

gcc -wall -o go go.o primes.o

and each of object files, go.o , primes.o checked against timestamp if got modified. example,

%.o: %.c $(deps) $(cc) $(cflags) -c -o $@ $<

expands go.o as: go.o : go.c primes.h

i.e. if go.o has timestamp before timestamps of either go.c or primes.h, rule fired. and, rule is:

gcc -wall -c -o go.o go.c

$< expands go.c (first dependency) in case

makefile