VHDL - Add operation between Signed -

VHDL - Add operation between Signed -

i'm new @ vhdl. i'm trying realize block diagram in next picture: code realize z^1 block (which delay) following:

library ieee; utilize ieee.std_logic_1164.all; utilize ieee.numeric_std.all; entity dff generic (n : integer:=16); port( d : in signed(n-1 downto 0); -- info input clk : in std_logic; -- clock input reset : in std_logic; -- reset input q : out signed(n-1 downto 0)); -- info output end dff; architecture behavioral of dff begin dff:process(clk) begin if (clk'event , clk='1') in 0 n-1 loop q(i) <= reset , d(i); end loop; end if; end process dff; end behavioral;

the code realize entire block diagram following:

library ieee; utilize ieee.std_logic_1164.all; utilize ieee.numeric_std.all; entity fir generic (n : integer:=16); port( clk : in std_logic; --clock signal reset : in std_logic; xin : in signed(n-1 downto 0); --input signal yout : out signed(n-1 downto 0) --filter output ); end fir; architecture fir_struct of fir component dff generic (n : integer:=16); port( d : in signed(n-1 downto 0); clk : in std_logic; reset : in std_logic; q : out signed(n-1 downto 0)); end component; signal y_delayed, add2_in1, add2_in2, y_temp : signed(n-1 downto 0) := (others => '0'); -- add2_in1 first input of adder (the input of block diagram) -- add2_in2 delayed output of adder -- y_temp output of adder -- y_delayed output of delay operation begin add2_in1 <= xin; y_temp <= add2_in1 + add2_in2; -- line giving me troubles delay1: dff port map(y_temp, clk, reset, y_delayed); yout <= y_temp; add2_in2 <= y_delayed; end fir_struct;

i highlighted line gives me troubles. tried remove , set first parameter of delay1 input xin (just seek if works or problem in line) , works (of course of study doesn't want, waveform behave expeted). testbench following:

library ieee; utilize ieee.std_logic_1164.all; utilize ieee.numeric_std.all; utilize ieee.std_logic_unsigned.all; entity iir_wav_tb end iir_wav_tb; architecture behavior of iir_wav_tb signal clk : std_logic := '0'; signal reset : std_logic := '1'; signal xin : signed(15 downto 0) := (others => '0'); signal yout : signed(15 downto 0) := (others => '0'); constant clk_period : time := 10 ns; begin -- instantiate unit under test (uut) uut: entity work.fir port map ( clk => clk, reset => reset, xin => xin, yout => yout); -- clock process definitions clk_process :process begin clk <= '0'; wait clk_period/2; clk <= '1'; wait clk_period/2; end process; -- stimulus process stim_proc: process begin xin <= to_signed(1,16); wait clk_period*1; xin <= to_signed(23,16); wait clk_period*1; end process; end

the waveform obtain following:

the problem when add together operation occurs, value of y_temp become '?' (the components of 16bits signal 'x'). think problem of inizialization, passing xin straight without adding won't rising problem. help me?

before start code, need remember vhdl create hardware , it's not software language. so, every process executed in parallel simulator. variables executed immediately.

second thing, don't initialize signals don't need initialization.

so, propose changes:

library ieee; utilize ieee.std_logic_1164.all; utilize ieee.numeric_std.all; entity dff generic (n : integer:=16); port( d : in signed(n-1 downto 0); -- info input clk : in std_logic; -- clock input reset : in std_logic; -- reset input q : out signed(n-1 downto 0)) -- info output end dff; architecture behavioral of dff begin dff:process(clk,reset) begin if (reset = '0') q <= (others => '0'); elsif (clk'event , clk='1') q <= d; end if; end process dff; end behavioral;

doing so, initialize add2_in2 within flip-flop (it's necessary reset @ begin going 0 1). don't need loop assign every bit.

library ieee; utilize ieee.std_logic_1164.all; utilize ieee.numeric_std.all; entity fir generic (n : integer:=16); port( clk : in std_logic; --clock signal reset : in std_logic; xin : in signed(n-1 downto 0); --input signal yout : out signed(n-1 downto 0) --filter output ); end fir; architecture fir_struct of fir component dff generic (n : integer:=16); port( d : in signed(n-1 downto 0); clk : in std_logic; reset : in std_logic; q : out signed(n-1 downto 0)); end component; signal y_delayed, y_temp : signed(n-1 downto 0); -- add2_in1 first input of adder (the input of block diagram) -- add2_in2 delayed output of adder -- y_temp output of adder -- y_delayed output of delay operation begin y_temp <= xin + y_delayed; delay1: dff port map(y_temp, clk, reset, y_delayed); yout <= y_temp; end fir_struct;

i think adder work. need update test-bench:

signal reset : std_logic; process begin reset <= '0'; wait 5 ns; reset <= '1'; wait; end process;

if forgot something, please inquire me.

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