Verilog code does not print desired output -

Verilog code does not print desired output -

can tell me why simple verilog programme doesn't print 4 want?

primitive confrontatore(output z, input x, input y); table 0 0 : 1; 0 1 : 0; 1 0 : 0; 1 1 : 1; endtable endprimitive

comparatore :

module comparatore (r, x, y); output wire r; input wire [21:0]x; input wire [21:0]y; wire [21:0]z; genvar i; generate for(i=0; i<22; i=i+1) begin confrontatore t(z[i],x[i],y[i]); end endgenerate assign r = & z; endmodule

commutatore :

module commutatore (uscita_commutatore, alpha); output wire [2:0]uscita_commutatore; input wire alpha; reg [2:0]temp; initial begin case (alpha) 1'b0 : assign temp = 3; 1'b1 : assign temp = 4; endcase end assign uscita_commutatore = temp; endmodule

prova:

module prova(); reg [21:0]in1; reg [21:0]in2; wire [2:0]uscita; wire uscita_comparatore; comparatore c(uscita_comparatore, in1, in2); commutatore c(uscita, uscita_comparatore); initial begin in1 = 14; $dumpfile("prova.vcd"); $dumpvars; $monitor("\n in1 %d in2 %d -> uscita %d uscita_comparatore %d \n", in1, in2, uscita, uscita_comparatore); #25 in2 = 14; #100 $finish; end endmodule

the issue in commutatore. using initial, means procedural block executed @ time 0. @ time 0, input alpha 1'bx, meaning temp not assigned anything. instead of initial, utilize always @* execute procedural block every time alpha changes.

generally should not assign statements in procedural blocks. legal verilog source of design bugs , synthesis back upwards limited.

always @* begin case (alpha) 1'b0 : temp = 3; 1'b1 : temp = 4; default: temp = 3'bx; // <-- optional : grab known unknown transitions endcase end

verilog