verilog - Xilinx loop has iterated 64 times error -

verilog - Xilinx loop has iterated 64 times error -

i writing code pipeline multiplication algorithm , while synthesizing using xilinx 10.1, getting next error:

"error:xst:1312 - loop has iterated 64 times. utilize "set -loop_iteration_limit xx" iterate more".

how can prepare or how can find out causes it?

based on info xilinx webpage:

this error occurs if xst encounters loop (typically "while loop") not have discrete termination. rather unrolling loop forever, xst fails error during hdl analysis. line number not provided, error reported within context of entity/module beingness analyzed.

you can solve issue adding e.g. set -loop_iteration_limit 256 .xst file in project. additional info can find here.

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