arm - Using multiple core on Zynq -

arm - Using multiple core on Zynq -

until today programming on single core, need run codes on multiple core. i'm researching 1 week , had questions this.

i'm using zynq 702, arm ds-5 , dstream way. , i'm trying achive while i'm using nowadays codes running on core0.

i did nil on core1, connected , want observe jumps 0xfffffff0 , value of address. didn't set interrupt handler targets core1. ok "observe" situation? or need configurations set? how can accomplish easiest way?

i connect core1 , observe state while programme continues on core0. there no application running on core1 way.. goes address 0x300, at address there wfe command , right after there b(ranch) command branching 0x300 again. loop , code stays 0.5second on wfe command, jumps next instruction b , branch wfe again......

i think core1 should remain right there after executing wfe command unless send event, not execute next b(ranch) command right? if so, mean core1 getting evets periodicly somewhere? connecting board dstream debugger causes events ?

if set value of address 0xfffffff0, makes core1 jump address @ 0xfffffff0, simple sev command plenty while core1 in wfe/wfi state? if 0xfffffff0 has value of 0x00000000, happens? core1 go calling wfe/wfi again? or else?

if core1 in wfe loop (state) sev cmd on core0 wakes core1. if come in wfe, go standby , sev wakeup, request scu can wakeup (for cache coherency operation in mp system).

note: after apu reset, core1 in wfe state, executing code 0xfffffe00 0xfffffff0

after boot, core1 in wfe state. if core1 gets sev jumps address stored @ 0xfffffff0. if update destination address after sev, core1 returns wfe state. because 0xfffffff0 has address of wfe instruction.

the right "startup sequence" is:

write address of core1 app 0xfffffff0 execute sev instruction

(have @ page 158 (6.1.10) in zynq-7000 programmable soc technical reference manual)

if 0xfffffff0 has value of 0x00000000 unpredictable results. (depending on cpu state).

arm multicore zynq