comparing t_data and rx_data for errors and giving the error value by total_error "verilog" -

comparing t_data and rx_data for errors and giving the error value by total_error "verilog" -

i have made bit error rate (ber) file in verilog. in ber module, have made total_error compares t_data , rx_data , totals number of errors gets comparing.

here code

`timescale 1ns / 1ps module ber ( clk, rstn, t_data, rx_data, total_error, enable ); //inputs input clk; input rstn; input [15 : 0] t_data; input [15 : 0] rx_data; input enable; //outputs output [15:0] total_error; reg [4:0] i; reg [15:0] subtotal, next_subtotal; assign total_error = subtotal; @(posedge clk) begin : comb next_subtotal = 0; (i = 0; < 16; = + 1) begin if (t_data[i] != rx_data[i] ) begin next_subtotal = next_subtotal + 1; end end end @(posedge clk) begin : dff if (rstn==1'b0) begin subtotal <= 7'b0000000; end else begin subtotal <= next_subtotal; end end endmodule

after making ber file, made file known ber_state_machine made state machine tranferring , receiving signals, instantiated ber file ber_state_machine file.

here code

// -------------------------------------------------------------------- `timescale 1ns/1ps module ber_state_machine ( clk, resetn, t_data [15:0], t_valid, t_ready, rx_data [15:0], rx_active, rx_valid, total_error ); //----------------------------------- input resetn, clk; // declaring inputs , outputs trasmit signals input [15 : 0] t_data; input t_valid; output t_ready; // declaring inputs , outputs receiving signals input [15 : 0] rx_data; input rx_active; input rx_valid; //----------------------------------- output [15 : 0] total_error; //----------------------------------- reg [6:0] sel; reg execute_in; reg t_ready; //------------------------------------------ ber uut ( .clk(clk), .rstn(resetn), .t_data(t_data), .rx_data(rx_data), .total_error(total_error), .enable(execute_in) ); //------------------------------------------ // making state machine here //inputs @ (posedge clk or negedge resetn) // state machine changing states begin if (resetn == 1'b1) // idle state begin sel <= 7'b000; // state 0 end else if (t_valid == 7'b1) begin sel <= 7'b001; // state 1 end else if (sel == 7'b001) begin sel <= 7'b010; // state 2 end else if (rx_active == 7'b1) begin sel <= 7'b011; // state 3 end else if (t_valid == 7'b1 && rx_valid == 7'b1) begin sel <= 7'b100; // state 4 end else if (sel == 7'b100) begin sel <= 7'b101; // state 5 end else if (t_valid == 2'b0 && rx_valid == 2'b0) begin sel <= 7'b100; // going state 4 end end // state machine //outputs @ (posedge clk) // outputs every state in state diagram begin case(sel) 7'b000 : execute_in = 2'b0; // state 0 7'b001 : t_ready = 2'b1; // state 1 7'b010 : t_ready = 2'b0; // state 2 7'b011 : execute_in = 2'b1; // state 3 7'b100 : t_ready = 2'b1; // state 4 7'b101 : t_ready = 2'b0; // state 5 endcase end endmodule

after this, made test bech see behavioral simulation. there few problems getting not able prepare due less verilog experience.

the t_data , rx_data undefined in simulation, after lastly bit, can see value each contains 0 - 15, undefined. dont know whats problem.

i dont see value in total_error, though set errors in t_data , rx_data dont see number of errors in total_error. can observe in simulation there errors in t_data , rx_data in final values.

here code test bench

`timescale 1ns / 1ps module test_bench(); //inputs reg execute_in; reg clk; reg resetn; //inputs transferring signals reg [15:0] t_data; reg t_valid; //inputs receiving signals reg [15:0] rx_data; reg rx_active; reg rx_valid; //outputs wire [15:0] total_error; wire t_ready; //instantiate unit under test (uut) ber_state_machine uut_ber ( .clk(clk), .resetn(resetn), .t_data(t_data), .t_valid(t_valid), .t_ready(t_ready), .rx_data(rx_data), .rx_active(rx_active), .rx_valid(rx_valid), .total_error(total_error) ); initial begin clk = 1'b0; resetn = 1'b1; repeat(4) #10 clk = ~clk; resetn = 1'b0; forever #10 clk = ~clk; end initial begin #100 execute_in = 0; #100 execute_in = 1; #100 t_valid = 1'b0; rx_active = 1'b0; #100 rx_valid = 1'b0; //************// #100 rx_active = 1'b1; t_valid = 1'b1; t_data[0] = 1'b0; // info 0 // create 0 error rx_valid = 1'b1; rx_data[0] = 1'b1; // create 0 error #50 t_valid = 1'b0; //************// #100 rx_active = 1'b1; t_valid = 1'b1; t_data[1] = 1'b1; // info 1 rx_valid = 1'b1; rx_data[1] = 1'b1; // create 0 error #50 t_valid = 1'b0; #100 rx_active = 1'b1; t_valid = 1'b1; t_data[2] = 1'b1; // info 2 rx_valid = 1'b1; rx_data[2] = 1'b1; // create 0 error #50 t_valid = 1'b0; #100 rx_active = 1'b1; t_valid = 1'b1; t_data[3] = 1'b0; // info 3 rx_valid = 1'b1; rx_data[3] = 1'b1; // create 0 error #50 t_valid = 1'b0; #100 rx_active = 1'b1; t_valid = 1'b1; t_data[4] = 1'b1; // info 4 rx_valid = 1'b1; rx_data[4] = 1'b1; // create 0 error #50 t_valid = 1'b0; #100 rx_active = 1'b1; t_valid = 1'b1; t_data[5] = 1'b1; // info 5 rx_valid = 1'b1; rx_data[5] = 1'b1; // create 0 error #50 t_valid = 1'b0; #100 rx_active = 1'b1; t_valid = 1'b1; t_data[6] = 1'b1; // info 6 rx_valid = 1'b1; rx_data[6] = 1'b1; // create 0 error #50 t_valid = 1'b0; #100 rx_active = 1'b1; t_valid = 1'b1; t_data[7] = 1'b1; // info 7 rx_valid = 1'b1; rx_data[7] = 1'b1; // create 0 error #50 t_valid = 1'b0; #100 rx_active = 1'b1; t_valid = 1'b1; t_data[8] = 1'b1; // info 8 rx_valid = 1'b1; rx_data[8] = 1'b0; // create 0 error #50 t_valid = 1'b0; #100 rx_active = 1'b1; t_valid = 1'b1; t_data[9] = 1'b1; // info 9 rx_valid = 1'b1; rx_data[9] = 1'b1; // create 0 error #50 t_valid = 1'b0; #100 rx_active = 1'b1; t_valid = 1'b1; t_data[10] = 1'b1; // info 10 rx_valid = 1'b1; rx_data[10] = 1'b1; // create 0 error #50 t_valid = 1'b0; #100 rx_active = 1'b1; t_valid = 1'b1; t_data[11] = 1'b1; // info 11 rx_valid = 1'b1; rx_data[11] = 1'b1; // create 0 error #50 t_valid = 1'b0; #100 rx_active = 1'b1; t_valid = 1'b1; t_data[12] = 1'b1; // info 12 rx_valid = 1'b1; rx_data[12] = 1'b1; // create 0 error #50 t_valid = 1'b0; #100 rx_active = 1'b1; t_valid = 1'b1; t_data[13] = 1'b1; // info 13 rx_valid = 1'b1; rx_data[13] = 1'b1; // create 0 error #50 t_valid = 1'b0; #100 rx_active = 1'b1; t_valid = 1'b1; t_data[14] = 1'b1; // info 14 rx_valid = 1'b1; rx_data[14] = 1'b1; // create 0 error #50 t_valid = 1'b0; #100 rx_active = 1'b1; t_valid = 1'b1; t_data[15] = 1'b1; // info 15 rx_valid = 1'b1; rx_data[15] = 1'b1; // create 0 error #50 t_valid = 1'b0; end endmodule

please help me out in this

your logic uses active-low reset. however, testbench starts reset signal de-asserted (resetn=1), asserts (resetn=0) after 40ns. think need invert polarity in testbench:

initial begin clk = 1'b0; resetn = 0; // assert active-low reset repeat(4) #10 clk = ~clk; resetn = ~resetn; // de-assert reset forever #10 clk = ~clk; end

verilog