Modelsim is not able to force some verilog signals -

Modelsim is not able to force some verilog signals -

i have verilog module must forcefulness signals, however, if signal has multiple bits , escaped name (need have space after signal) not possible because modelsim doesn't recognize bit of signal. generated verilog module ise post-synthesis , i'm running on mentor's modelsim.

multibit signal: {/tb/.../\something/name [0]} . how modelsim tries name bit of signal, not able find it. returns "(vish-4014) no objects found matching" error when launching command uses signal's bit (the whole signal works, need forcefulness single bit)

singlebit signal: {/tb/.../\something/name } (this works)

what can create modelsim forcefulness bits signals? (just beingness able utilize other command on bits works, because need know how can read successfully).

verilog modelsim